CPLD

by mrengstad.
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2 layer board of 0.70x2.00 inches (17.88x50.90 mm).
Shared on May 3rd, 2016 21:31.

A simple breakout for the Xilinx XC9572 CPLD

The only additional component is the 3.3V LDO regulator. If you already have 3.3V available, a pin is available to bypass it. Inputs and outputs are 3.3V if you insert a jumper; otherwise, the outputs are powered from the VCCIO pin. While the IO is 5V tolerant, the VCCIO must be less than 3.3V, for instance, 2.5V or 1.8V.

The breakout tested fine, and it works like a charm.

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