mntmn / amiga2000-gfxcard

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MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Verilog 854 39 Built by
nvdla / hw

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RTL, Cmodel, and testbench for NVDLA

Verilog 567 202 Built by
cliffordwolf / picorv32

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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 544 125 Built by
VerticalResearchGroup / miaow

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An open source GPU based off of the AMD Southern Islands ISA.

Verilog 449 106 Built by
parallella / oh

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Silicon proven Verilog library for IC and FPGA designers

Verilog 371 120 Built by
SI-RISCV / e200_opensource

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The Ultra-Low Power RISC Core

Verilog 262 94 Built by
analogdevicesinc / hdl

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HDL libraries and projects

Verilog 254 511 Built by
jmahler / mips-cpu

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MIPS CPU implemented in Verilog

Verilog 207 94 Built by
kramble / FPGA-Litecoin-Miner

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A litecoin scrypt miner implemented with FPGA on-chip memory.

Verilog 206 98 Built by
openrisc / mor1kx

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mor1kx - an OpenRISC 1000 processor IP core

Verilog 199 85 Built by
FPGAwars / icezum

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🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Verilog 198 52 Built by
NetFPGA / netfpga

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NetFPGA 1G infrastructure and gateware

Verilog 171 101 Built by
ZipCPU / zipcpu

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A small, light weight, RISC CPU soft core

Verilog 162 20 Built by
Obijuan / open-fpga-verilog-tutorial

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Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

Verilog 158 65 Built by
madcowswe / ODriveHardware

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High performance motor control

Verilog 150 57 Built by
alexforencich / verilog-ethernet

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Verilog Ethernet components

Verilog 148 51 Built by
zhemao / ez8

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The Easy 8-bit Processor

Verilog 146 22 Built by
marmolejo / zet

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Open source implementation of a x86 processor

Verilog 146 46 Built by
dtysky / FPGA-Imaging-Library

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An open source library for image processing on FPGA.

Verilog 142 82 Built by
sergeykhbr / riscv_vhdl

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VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

Verilog 137 35 Built by
SymbiFlow / prjxray

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Documenting the Xilinx 7-series bit-stream format.

Verilog 127 13 Built by
seldridge / verilog

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Repository for basic (and not so basic) Verilog blocks with high re-use potential

Verilog 121 52 Built by
cliffordwolf / riscv-formal

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RISC-V Formal Verification Framework

Verilog 117 6 Built by
brianbennett / fpga_nes

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FPGA-based Nintendo Entertainment System Emulator

Verilog 115 37 Built by
ridecore / ridecore

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RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog 108 23 Built by