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Caffe to VHDL - by DREAM research group
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A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…
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A work-in-progress for what is to be a software-free web server for static content.
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Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
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VHDL 2008/93/87 simulator
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GPL v3 2D/3D graphics engine in verilog
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Community created parallella projects
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Parallella board design files
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VUnit is a unit testing framework for VHDL/SystemVerilog
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GameCube Digital AV converter
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Core sources and tools for the MIST board
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IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
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Arduino MIPI DSI Shield
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RISC-V by VectorBlox
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Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
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A 32-bit RISC-V / MIPS ISA retargetable CPU core
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A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able p…
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Space Invaders game implemented with VHDL
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An implementation of DisplayPort protocol for FPGAs
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Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
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FPGA-based HDMI ambient lighting
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A pipelined RISCV implementation in VHDL
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The Zylin ZPU
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Open Source 4k CSI-2 Rx core for Xilinx FPGAs
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ZPUino HDL implementation
