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veripool / verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Verilog • Built by
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VerticalResearchGroup / miaow
An open source GPU based off of the AMD Southern Islands ISA.
Verilog • Built by
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kramble / FPGA-Litecoin-Miner
A litecoin scrypt miner implemented with FPGA on-chip memory.
Verilog • Built by
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marmolejo / zet
Open source implementation of a x86 processor
Verilog • Built by
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zhemao / ez8
The Easy 8-bit Processor
OCaml • Built by
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parallella / oh
Open hardware library for chip and FPGA designers (verilog)
Verilog • Built by
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m-labs / milkymist
SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
Verilog • Built by
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openrisc / mor1kx
mor1kx - an OpenRISC 1000 processor IP core
Verilog • Built by
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NetFPGA / netfpga
NetFPGA 1G infrastructure and gateware
Verilog • Built by
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gardners / c65gs
FPGA-based C64 Accelerator / C65 like computer
Verilog • Built by
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Arlet / verilog-6502
A Verilog HDL model of the MOS 6502 CPU
Verilog • Built by
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ngzhang / Icarus
DUAL Spartan6 Development Platform
Verilog • Built by
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brianbennett / fpga_nes
FPGA-based Nintendo Entertainment System Emulator
Verilog • Built by
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analogdevicesinc / hdl
HDL libraries and projects
Verilog • Built by
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jmahler / mips-cpu
MIPS CPU implemented in Verilog
Verilog • Built by
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andrejbauer / Homotopy
Homotopy theory in Coq.
Verilog • Built by
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jamieiles / oldland-cpu
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Verilog • Built by
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dtysky / FPGA-Imaging-Library
An open source library for image processing on FPGA.
Verilog • Built by
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openrisc / orpsoc-cores
Core description files for FuseSoC
Verilog • Built by
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teknohog / Xilinx-Serial-Miner
Bitcoin miner for Xilinx FPGAs
Verilog • Built by
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strigeus / fpganes
NES in Verilog
Verilog • Built by
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m-labs / lm32
LatticeMico32 soft processor
Verilog • Built by
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maidenone / ORGFXSoC
An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
Verilog • Built by
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ucb-bar / fpga-zynq
Support for Rocket Chip on Zynq FPGAs
Verilog • Built by
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tkimva / ucr-eecs168
EECS168 Introduction to VLSI Design Winter 2016 @ UCR
Verilog • Built by
